Semiconductor package and method of fabricating the same

ABSTRACT

Provided is a semiconductor package and a method of manufacturing the same, wherein in the semiconductor package, an area on a surface of a heat release metal layer pressed by a molding die is expanded and the molding die directly and uniformly compresses an upper substrate and/or a lower substrate, each of which does not include heat release posts so that contamination of a substrate occurring due to a molding resin may be prevented and molding may be stably performed.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2022-0011343, filed on Jan. 26, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor package and a method of manufacturing the same, wherein in the semiconductor package, an area on a surface of a heat release metal layer pressed by a molding die is expanded and the molding die directly and uniformly compresses an upper substrate and/or a lower substrate, each of which does not include heat release posts so that contamination of a substrate occurring due to a molding resin may be prevented and molding may be stably performed.

BACKGROUND ART

In general, a semiconductor package includes a semiconductor chip installed on a lower substrate and/or an upper substrate, a conductor which is a metal post functioning as a space bonded onto the semiconductor chip, a lead frame applying an electrical signal from the outside, a package housing molded by a sealing member, and heat release posts exposed to the lower substrate and/or the upper substrate. Referring to FIG. 1A, while a package housing 10 is molded, mold dies 20 only press a part of heat release metal layers 31 and 41, for example, the edges, by avoiding heat release posts 32 and 42 of a lower substrate 30 and/or an upper substrate 40. Accordingly, the package housing 10 is formed.

When the package housing 10 is formed as described above, pressurization from the mold die 20 is not uniform and a pressing force applied to the heat release metal layers 31 and 41 is weakened as illustrated in FIG. 1B. Accordingly, a molding resin 11 overflows toward the heat release metal layers 31 and 41 and thus, the substrate is contaminated so as to affect stability and reliability of the semiconductor package.

In this regard, there is a demand for the technique that may expand and uniformly compress an area on a surface of a heat release metal layer pressed by a molding die so as to prevent contamination of the substrate occurring due to a molding resin and to stably perform molding.

DISCLOSURE Technical Problem

The present invention provides a semiconductor package and a method of manufacturing the same, wherein in the semiconductor package, an area on a surface of a heat release metal layer pressed by a molding die is expanded and the molding die directly and uniformly compresses an upper substrate and/or a lower substrate, each of which does not include heat release posts, so that contamination of a substrate occurring due to a molding resin may be prevented and molding may be stably performed.

Technical Solution

According to an aspect of the present invention, there is provided a semiconductor package including: an upper substrate or a lower substrate each of which comprises a plurality of heat release posts protruded and arranged thereon; semiconductor chips joined onto the upper substrate or the lower substrate and connected by electrical signal lines; lead frames electrically connected to the upper substrate or the lower substrate; and a molding housing partially or entirely covering a region of the upper substrate or the lower substrate to which the semiconductor chips are not joined, wherein the heat release posts are extended from the lower surface, the upper surface, or the lower and upper surfaces of the upper substrate or the lower substrate and exposed to the surface of the molding housing by a certain height, one or more mold distances D2 interposed between the heat release posts, which directly contact the upper substrate or the lower substrate by the molding die, are greater than one or more post distances D1 interposed between the heat release posts, lines arranged for the surface of the molding die to contact the upper substrate or the lower substrate include any one of a penetration line L1 and a nonpenetration line L2, wherein the penetration line L1 entirely penetrates the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction, and the nonpenetration line L2 is blocked by the heat release posts and thereby, does not partially penetrate the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction.

The mold distances D2 may be greater than the post distances D1 by two times or above.

The mold distances D2 may be in the range of 1 mm through 300 mm.

The heat release posts may be formed in circular columns, elliptic cylinders, or polygonal columns.

The heat release posts may be formed of a metal or contain 40% or more of a metal component.

The upper substrate or the lower substrate may include one or more insulating layers.

The upper substrate or the lower substrate may include one or more heat release metal layers, on which the heat release posts are arranged, one or more insulating layers on the heat release metal layers, one or more metal pattern layers electrically connected to the semiconductor chips on the insulating layers, and one or more conductive bonding layers formed on the upper surface or the lower surface of the semiconductor chips.

The heat release posts may be formed of a material which is same as that of the heat release metal layers.

The electrical signal lines may be surface-bonding type conductive clips or post-shaped conductive spacers.

The molding housing may be formed of an Epoxy Molding Compound (EMC).

The heat release posts may include a semiconductor cooling system joined to the upper part or the lower part thereof and a coolant circulating the semiconductor cooling system directly may contact the heat release posts.

The coolant may include cooling water, a coolant fluid, refrigerant gas, or air.

The insulating layers may be formed of a single material comprising Al₂O₃, AlN, Si₃N₄, or SiC or a composite material including any one of Al₂O₃, AIN, Si₃N₄, and SiC.

The semiconductor chips may be applied to on board chargers (OBC), inverters, or converters.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor package including: preparing an upper substrate or a lower substrate each of which comprises a plurality of heat release posts protruded and arranged thereon; joining semiconductor chips on the upper substrate or the lower substrate and connecting together by using electrical signal lines; electrically connecting lead frames to the upper substrate or the lower substrate; and partially or entirely covering a region of the upper substrate or the lower substrate, to which the semiconductor chips are not joined, with a molding housing, wherein the heat release posts are extended from the lower surface, the upper surface, or the lower and upper surfaces of the upper substrate or the lower substrate and exposed to the surface of the molding housing by a certain height, one or more mold distances D2 interposed between the heat release posts, which directly contact the upper substrate or the lower substrate by the molding die, are greater than one or more post distances D1 interposed between the heat release posts, lines arranged for the surface of the molding die to contact the upper substrate or the lower substrate include any one of a penetration line L1 and a nonpenetration line L2, wherein the penetration line L1 entirely penetrates the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction, and the nonpenetration line L2 is blocked by the heat release posts and thereby, does not partially penetrate the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction, and wherein while the molding housing is molded by the molding die, the molding die compresses one or more penetration lines L1 or one or more nonpenetration lines L2 to form the molding housing.

The mold distances D2 may be greater than the post distances D1 by two times or above.

The mold distances D2 may be in the range of 1 mm through 300 mm.

The heat release posts may be formed of a metal or contain 40% or more of a metal component.

The upper substrate or the lower substrate may include one or more heat release metal layers, on which the heat release posts are arranged, one or more insulating layers on the heat release metal layers, one or more metal pattern layers electrically connected to the semiconductor chips on the insulating layers, and one or more conductive bonding layers formed on the upper surface or the lower surface of the semiconductor chips.

The heat release posts may be formed of a material which is same as that of the heat release metal layers.

Advantageous Effects

According to the present invention, areas on the surfaces of the heat release metal layers pressed by the molding die are expanded and the molding die directly and uniformly compresses the upper substrate and/or the lower substrate, each of which does not include the heat release posts, so that contamination of the substrate occurring due to a molding resin may be prevented and molding may be stably performed.

DESCRIPTION OF DRAWINGS

FIG. 1 illustrates a semiconductor package according to a prior art;

FIG. 2 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention;

FIG. 3 illustrates a joining structure between a substrate of the semiconductor package in FIG. 2 and a molding die;

FIG. 4 is a cross-sectional view of the semiconductor package in FIG. 2 according to a second embodiment of the present invention;

FIG. 5 is a cross-sectional view of the semiconductor package in FIG. 2 according to a third embodiment of the present invention;

FIG. 6 is a cross-sectional view of the semiconductor package in FIG. 2 according to a fourth embodiment of the present invention;

FIG. 7 illustrates a joining structure between heat release posts of the semiconductor package in FIG. 2 and a molding die;

FIGS. 8 and 9 illustrate various examples of penetration lines and non-penetration lines in the semiconductor package of FIG. 2 ; and

FIG. 10 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.

MODE FOR INVENTION

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

A semiconductor package according to an embodiment of the present invention includes an upper substrate 110 and/or a lower substrate 120 each of which includes a plurality of heat release posts 111 and 121 protruded and arranged thereon, semiconductor chips 130 joined onto the upper substrate 110 and/or the lower substrate 120 and connected by electrical signal lines 131, lead frames 140 electrically connected to the upper substrate 110 and/or the lower substrate 120, and a molding housing 150 partially or entirely covering a region of the upper substrate 110 and/or the lower substrate 120 to which the semiconductor chips 130 are not joined. Here, the heat release posts 111 and 121 are extended from the lower surface, the upper surface, or the lower and upper surfaces of the upper substrate 110 and/or the lower substrate 120 and exposed to the surface of the molding housing 150 by a certain height. Also, mold distances D2 within a molding die 160 used to shape the molding housing 150 is greater than post distances D1 between the heat release posts 111 and 121. Lines arranged for the surface of the molding die 160 to contact the upper substrate 110 or the lower substrate 120 include a penetration line L1 and/or a nonpenetration line L2, wherein the penetration line L1 entirely penetrates the surfaces of the upper substrate 110 and/or the lower substrate 120 in a horizontal direction, and the nonpenetration line L2 is blocked by the heat release posts 111 and 121 and thereby, does not partially penetrate the surfaces of the upper substrate 110 and/or the lower substrate 120 in a horizontal direction. Accordingly, the molding die 160 may directly and uniformly compress the upper substrate 110 and/or the lower substrate 120 where the heat release posts 111 and 121 are not arranged.

Hereinafter, the semiconductor package described above will be described in more detail with reference to FIGS. 2 through 9 .

First, referring to FIGS. 2 and 3 , the plurality of heat release posts 111 and 121 used to radiate heat is protruded from and arranged on the surface of the upper substrate 110 or the lower substrate 120 and thereby, heat transmitted from the upper substrate 110 or the lower substrate 120 is radiated to the outside.

Here, the heat release posts 111 and 121 are extended from the lower surface, the upper surface, or the upper and lower surfaces of the upper substrate 110 and/or the lower substrate 120 and stand upright by being uniformly exposed to the surface of the molding housing 150 at a certain height.

Also, in regard to the arrangement of the heat release posts 111 and 121 as illustrated in FIGS. 2 and 3 , one or more mold distances D2 interposed between the heat release posts 111 and 121, which directly contact the upper substrate 110 and/or the lower substrate 120 by the molding die 160, are greater than one or more post distances D1 interposed between the heat release posts 111 and 121. In addition, as illustrated in FIGS. 8 and 9 , lines arranged for the surface of the molding die 160 to contact the upper substrate 110 or the lower substrate 120 may include the penetration line L1 and/or the nonpenetration line L2, wherein the penetration line L1 entirely penetrates the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction, and the nonpenetration line L2 is blocked by the heat release posts 111 and 121 and thereby, does not partially penetrate the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction.

In this regard, while the molding housing 150 is molded by the molding die 160, the molding die 160 may directly compress heat release metal layers 113 and 123 of the upper substrate 110 and/or the lower substrate 120 where the heat release posts 111 and 121 are not arranged. Accordingly, pressure applied to the substrates is raised and uniform and thus, a molding resin may be prevented from overflowing toward the surfaces of the heat release metal layers 113 and 123. Therefore, quality stability may be improved.

That is, compared with the arrangement where the heat release posts 111 and 121 are close to each other, areas on surfaces of the heat release metal layers 113 and 123 pressed by the molding die 160 may be expanded and molding may be stably performed by using the penetration line L1 and the nonpenetration line L2, where a part of the heat release posts 111 and 121 is removed for the surface of the molding die 160 to contact the upper substrate 110 or the lower substrate 120.

More specifically, various modifications are available for expanding the areas on the surfaces of the heat release metal layers 113 and 123 pressed by the molding die 160. Referring to FIG. 8A, the penetration line L1 may be formed in an X-axis direction based on the surface of the substrate. Referring to FIG. 8B, the penetration line L1 may be formed in an X-axis direction and a Y-axis direction based on the surface of the substrate. Referring to FIG. 8C, a pair of nonpenetration lines L2 facing each other may be formed in an X-axis direction based on the surface of the substrate. Referring to FIG. 9D, two pairs of nonpenetration lines L2 respectively facing each other may be each formed in an X-axis direction and a Y-axis direction based on the surface of the substrate. Referring to FIG. 9E, a pair of nonpenetration lines L2 facing each other may be formed in an X-axis direction and the penetration line L1 may be formed in a Y-axis direction. Also, in contrast to this, a pair of nonpenetration lines L2 facing each other may be formed in a Y-axis direction and the penetration line L1 may be formed in an X-axis direction.

The mold distances D2 are greater than the post distances D1 by two times or above and thus, the areas on the surfaces of the heat release metal layers 113 and 123, which may be sufficiently pressed by the molding die 160, may be secured. For example, the mold distances D2 may be in the range of 1 mm through 300 mm.

The heat release posts 111 and 121 may be formed in various forms such as circular columns, elliptic cylinders, or polygonal columns. Also, the heat release posts 111 and 121 may be formed of a metal having excellent thermal conductivity or may contain 40% or more of a metal component having excellent thermal conductivity. The heat release posts 111 and 121 may be formed of a material which is same as that of the heat release metal layers 113 and 123. For example, the heat release posts 111 and 121 may be formed of a single material including Cu or Al, an alloy material containing 50% or more of Cu or Al, or a ceramic material.

As illustrated in an enlarged view of FIG. 3 , the upper substrate 110 and/or the lower substrate 120 may each include one or more insulating layers 112 and 122, wherein the insulating layers 112 and 122 may be formed of a single material including A l₂O₃, AIN, Si₃N₄, or SiC or a composite material including at least one of Al₂O₃, AlN, Si₃N₄, and SiC.

Also, the upper substrate 110 and/or the lower substrate 120 may include one or more heat release metal layers 113 and 123, on which the heat release posts 111 and 121 are respectively arranged, one or more insulating layers 112 and 122 respectively formed on the heat release metal layers 113 and 123, one or more metal pattern layers 114 and 124 formed on the insulating layers 112 and 122 and electrically connected to the semiconductor chips 130, and one or more conductive bonding layers 125 formed on the upper surface and/or the lower surface of the semiconductor chip 130.

The electrical signal lines 131, which electrically connect the semiconductor chips 130 to the metal pattern layers 114 and 124, may each be a wire, a surface-bonding type conductive clip 132 as in FIG. 4 , or a post-shaped conductive spacer 126.

The heat release posts 111 and 121 may be exposed to one surface or both surfaces of the molding housing 150 according to a structure of the substrate including a single-sided substrate or a both-sided substrate. For example, referring to FIG. 5 , the lower substrate 120 may include one or more first heat release metal layers 123 a, on which the heat release posts 121 are arranged, a second heat release metal layer 123 c formed by joining a bonding layer 123 b on the first heat release metal layer 123 a, one or more insulating layers 122, one or more metal pattern layers 124 electrically connected to the semiconductor chips 130 on the insulating layers 122, and one or more conductive bonding layers 125 formed on the upper surface or the lower surface of the semiconductor chips 130.

Also, referring to FIG. 6 , the lower substrate 120 may include one or more heat release metal layer 123, on which the heat release posts 121 are arranged, a non-conductive bonding layer 127 functioning as an insulating layer, one or more metal pattern layers 124 electrically connected to the semiconductor chips 130 on the non-conductive bonding layer 127, and one or more conductive bonding layers 125 formed on the upper surface or the lower surface of the semiconductor chips 130.

Next, the semiconductor chips 130 are bonded and installed onto the upper substrate 110 and/or the lower substrate 120 and are electrically connected to the metal pattern layers 114 and 124 of the upper substrate 110 and/or the lower substrate 120 by the electrical signal lines 131. Accordingly, an external signal may be applied to the semiconductor chips 130.

Also, the semiconductor chips 130 may be applied to devices such as inverters, converters, or on board chargers (OBC) which convert and control power by using Insulated Gate Bipolar Transistors (IGBT) or Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) which are power semiconductor chips.

Next, the lead frames 140 contact and are electrically connected to the metal pattern layers 114 and 124 of the upper substrate 110 and/or the lower substrate 120 and receive an external signal.

The molding housing 150 partially or entirely covers a region of the upper substrate 110 and/or the lower substrate 120 to which the semiconductor chips 130 are not joined. Accordingly, while a structural form between the upper substrate 110 and the lower substrate 120 maintains, the upper substrate 110 and the lower substrate 120 are electrically insulated from each other.

Here, as the molding housing 150 is formed of an Epoxy Molding Compound (EMC), PBT, or PPS for insulation, the molding housing 150 covers, protects, and insulates at least a part of an inner circuit.

A semiconductor cooling system is watertight and is joined to the upper part (or the lower part) of the heat release posts 111 and 121 and a coolant circulating the semiconductor cooling system directly contact the uprightly-formed heat release posts 111 and 121. In this regard, an area contacting the coolant is enlarged so as to improve heat release efficiency. The coolant may be cooling water, a coolant fluid, refrigerant gas, or air. However, the present invention is not limited thereto and the coolant may include all kinds of cooling medium which is cold. Also, a cooling method may be water cooling or air cooling.

FIG. 10 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention. The method of manufacturing a semiconductor package will be described in more detail below with reference to FIG. 10 .

The method includes preparing the upper substrate 110 and/or the lower substrate 120, on which the plurality of heat release posts 111 and 121 is protruded and arranged in a matrix form, in operation S110, joining the semiconductor chips 130 on the upper substrate 110 and/or the lower substrate 120 and connecting together by using the electrical signal lines 131 in operation S120, electrically connecting the lead frames 140 to the upper substrate 110 and/or the lower substrate 120 in operation S130, and partially or entirely covering a region of the upper substrate 110 and/or the lower substrate 120, to which the semiconductor chips 130 are not joined, in operation S140.

Here, in preparing the substrates in operation S110, the heat release posts 111 and 121 are extended from the lower surface, the upper surface, or the lower and upper surfaces of the upper substrate 110 and/or the lower substrate 120 and stand upright by being exposed to the surface of the molding housing 150 at a certain height. Also, the mold distances D2 within the molding die 160 used to shape the molding housing 150 is greater than the post distances D1 between the heat release posts 111 and 121. Lines arranged to partially or entirely contact the surface of the molding die 160 include the penetration line L1 and/or the nonpenetration line L2, wherein the penetration line L1 penetrates the entire surface of the upper substrate 110 and/or the lower substrate 120 in a horizontal direction, and the nonpenetration line L2 is blocked by the heat release posts 111 and 121 and thereby, does not penetrate a part of the upper substrate 110 and/or the lower substrate 120 in a horizontal direction. While the molding housing 150 is molded by the molding die 160, the molding die 160 compresses one or more penetration lines L1 and/or one or more nonpenetration lines L2 to form the molding housing 150. Accordingly, the molding die 160 may directly and uniformly compress the upper substrate 110 and/or the lower substrate 120 where the heat release posts 111 and 121 are not arranged. In this regard, pressure applied to the substrates is raised and uniform and thus, a molding resin may be prevented from overflowing toward the surfaces of the heat release metal layers 113 and 123. Therefore, quality stability may be improved.

Here, the mold distances D2 may be greater than the post distances D1 by two times or above and the mold distances D2 may be in the range of 1 mm through 300 mm.

The heat release posts 111 and 121 may be formed of a metal having excellent thermal conductivity or may contain 40% or more of a metal component having excellent thermal conductivity.

The upper substrate 110 and/or the lower substrate 120 may include one or more heat release metal layers 113 and 123, on which the heat release posts 111 and 121 are respectively arranged, one or more insulating layers 112 and 122 respectively formed on the heat release metal layers 113 and 123, one or more metal pattern layers 114 and 124 formed on the insulating layers 112 and 122 and electrically connected to the semiconductor chips 130, and one or more conductive bonding layers 125 formed on the upper surface and/or the lower surface of the semiconductor chip 130. The heat release posts 111 and 121 may be formed of a material which is same as that of the heat release metal layers 113 and 123.

According to the semiconductor package and the method of manufacturing the same described above, areas on the surfaces of the heat release metal layers pressed by the molding die are expanded and the molding die directly and uniformly compresses the upper substrate or the lower substrate, each of which does not include the heat release posts, so that contamination of the substrate occurring due to a molding resin may be prevented and molding may be stably performed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims. 

What is claimed is:
 1. A semiconductor package comprising: an upper substrate or a lower substrate each of which comprises a plurality of heat release posts protruded and arranged thereon; semiconductor chips joined onto the upper substrate or the lower substrate and connected by electrical signal lines; lead frames electrically connected to the upper substrate or the lower substrate; and a molding housing partially or entirely covering a region of the upper substrate or the lower substrate to which the semiconductor chips are not joined, wherein the heat release posts are extended from the lower surface, the upper surface, or the lower and upper surfaces of the upper substrate or the lower substrate and exposed to the surface of the molding housing by a certain height, one or more mold distances D2 interposed between the heat release posts, which directly contact the upper substrate or the lower substrate by the molding die, are greater than one or more post distances D1 interposed between the heat release posts, lines arranged for the surface of the molding die to contact the upper substrate or the lower substrate include any one of a penetration line L1 and a nonpenetration line L2, wherein the penetration line L1 entirely penetrates the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction, and the nonpenetration line L2 is blocked by the heat release posts and thereby, does not partially penetrate the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction.
 2. The semiconductor package of claim 1, wherein the mold distances D2 are greater than the post distances D1 by two times or above.
 3. The semiconductor package of claim 1, wherein the mold distances D2 are in the range of 1 mm through 300 mm.
 4. The semiconductor package of claim 1, wherein the heat release posts are formed in circular columns, elliptic cylinders, or polygonal columns.
 5. The semiconductor package of claim 1, wherein the heat release posts are formed of a metal or contain 40% or more of a metal component.
 6. The semiconductor package of claim 1, wherein the upper substrate or the lower substrate comprises one or more insulating layers.
 7. The semiconductor package of claim 1, wherein the upper substrate or the lower substrate comprises one or more heat release metal layers, on which the heat release posts are arranged, one or more insulating layers on the heat release metal layers, one or more metal pattern layers electrically connected to the semiconductor chips on the insulating layers, and one or more conductive bonding layers formed on the upper surface or the lower surface of the semiconductor chips.
 8. The semiconductor package of claim 7, wherein the heat release posts are formed of a material which is same as that of the heat release metal layers.
 9. The semiconductor package of claim 1, wherein the electrical signal lines are surface-bonding type conductive clips or post-shaped conductive spacers.
 10. The semiconductor package of claim 1, wherein the molding housing is formed of an Epoxy Molding Compound (EMC).
 11. The semiconductor package of claim 1, wherein the heat release posts comprise a semiconductor cooling system joined to the upper part or the lower part thereof and a coolant circulating the semiconductor cooling system directly contacts the heat release posts.
 12. The semiconductor package of claim 11, wherein the coolant comprises cooling water, a coolant fluid, refrigerant gas, or air.
 13. The semiconductor package of claim 6, wherein the insulating layers are formed of a single material comprising Al₂O₃, AIN, Si₃N₄, or SiC or a composite material comprising any one of Al₂O₃, AIN, Si₃N₄, and SiC.
 14. The semiconductor package of claim 1, wherein the semiconductor chips are applied to on board chargers (OBC), inverters, or converters.
 15. A method of manufacturing a semiconductor package comprising: preparing an upper substrate or a lower substrate each of which comprises a plurality of heat release posts protruded and arranged thereon; joining semiconductor chips on the upper substrate or the lower substrate and connecting together by using electrical signal lines; electrically connecting lead frames to the upper substrate or the lower substrate; and partially or entirely covering a region of the upper substrate or the lower substrate, to which the semiconductor chips are not joined, with a molding housing, wherein the heat release posts are extended from the lower surface, the upper surface, or the lower and upper surfaces of the upper substrate or the lower substrate and exposed to the surface of the molding housing by a certain height, one or more mold distances D2 interposed between the heat release posts, which directly contact the upper substrate or the lower substrate by the molding die, are greater than one or more post distances D1 interposed between the heat release posts, lines arranged for the surface of the molding die to contact the upper substrate or the lower substrate include any one of a penetration line L1 and a nonpenetration line L2, wherein the penetration line L1 entirely penetrates the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction, and the nonpenetration line L2 is blocked by the heat release posts and thereby, does not partially penetrate the surface of the upper substrate in a horizontal direction, the surface of the lower substrate in a horizontal direction, or each surface on the upper substrate and the lower substrate in a horizontal direction, and wherein while the molding housing is molded by the molding die, the molding die compresses one or more penetration lines L1 or one or more nonpenetration lines L2 to form the molding housing.
 16. The method of claim 15, wherein the mold distances D2 are greater than the post distances D1 by two times or above.
 17. The method of claim 15, wherein the mold distances D2 are in the range of 1 mm through 300 mm.
 18. The method of claim 15, wherein the heat release posts are formed of a metal or contain 40% or more of a metal component.
 19. The method of claim 15, wherein the upper substrate or the lower substrate comprises one or more heat release metal layers, on which the heat release posts are arranged, one or more insulating layers on the heat release metal layers, one or more metal pattern layers electrically connected to the semiconductor chips on the insulating layers, and one or more conductive bonding layers formed on the upper surface or the lower surface of the semiconductor chips.
 20. The method of claim 19, wherein the heat release posts are formed of a material which is same as that of the heat release metal layers. 